Sequential Logic

The SystemVerilog always_ff procedure can be used to model synthesizable sequential logic behavior. For example:

always_ff @(posedge clock iff reset == 0 or posedge reset) begin
r1 <= reset ? 0 : r2 + 1;
...
end

The always_ff block imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process.

Software tools can perform additional checks to warn if the behavior within an always_ff procedure does not represent sequential logic.