`timescale 1ns/1ns
module ram(wr_ad,rd_ad,wr_en,rd_en,clk,wr_dat,rd_dat);
//parameter addr_width=4;
//parameter depth=16;
//parameter data_width=16;
input wr_en,rd_en,clk;
input [3:0] wr_ad;
input [3:0] rd_ad;
input [15:0] wr_dat;
output [15:0] rd_dat;
reg [15:0] rd_dat;
reg [15:0] mem[0:15];
//memory write
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ad]<=wr_dat;
end
//memory read
always @ (posedge clk)
begin
if(rd_en)
begin
rd_dat<=mem[rd_ad];
end
end
endmodule
//read_write_logic
`timescale 1ns/1ns
module rd_wr_logic(wr_addr,rd_addr,rst,clk,wr_en,rd_en,fifo_full,fifo_empty);
input rst,clk;
input wr_en,rd_en;
output[3:0]wr_addr,rd_addr;
output fifo_full, fifo_empty;
reg [4:0]wr_ptr;
reg [4:0]rd_ptr;
reg fifo_full, fifo_empty;
wire [3:0]wr_addr,rd_addr;
//extract read and write address from ptrs
assign rd_addr = rd_ptr[3:0];
assign wr_addr = wr_ptr[3:0];
//fifo full status
//assign fifo_full = ((wr_ptr[3:0]==rd_ptr[3:0]) && (wr_ptr[4]!=rd_ptr[4]));
//assign fifo_empty = (rd_ptr == wr_ptr);
//write pointer gen logic
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
wr_ptr <= 5'b0000;
rd_ptr <= 5'b0000;
end
else
if(wr_en)
wr_ptr <= wr_ptr+1;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
rd_ptr <= 5'b0000;
end
else if(rd_en)
rd_ptr <= rd_ptr+1;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
fifo_full <= 1'b0;
fifo_empty <= 1'b1;
end
else
begin
if((wr_ptr[3:0]==rd_ptr[3:0]) && (wr_ptr[4]!=rd_ptr[4]))
fifo_full <= 1'b1;
else
fifo_full <= 1'b0;
if(rd_ptr == wr_ptr)
fifo_empty <= 1'b1;
else
fifo_empty <= 1'b0;
end
end
endmodule
//fifo_top_module
`timescale 1ns/1ns
module fifo_top(clk,rst,wr_enable,rd_enable,wr_data,fifo_full1,fifo_empty1,rd_data);
input clk,rst;
input [15:0]wr_data;
input wr_enable, rd_enable;
//input [3:0]wr_adre,rd_adre;
output [15:0]rd_data;
output fifo_full1, fifo_empty1;
//reg [15:0] rd_data;
wire [3:0]wr_addr,rd_addr;
//wire [4:0] rd_ptr1;
//wire [4:0] wr_ptr1;
ram r(.wr_ad(wr_addr), .rd_ad(rd_addr), .wr_en(wr_enable), .rd_en(rd_enable), .clk(clk), .wr_dat(wr_data), .rd_dat(rd_data));
rd_wr_logic wlogic(.rd_addr(rd_addr),.rst(rst), .clk(clk), .wr_en(wr_enable), .rd_en(rd_enable), .wr_addr(wr_addr), .fifo_full(fifo_full1), .fifo_empty(fifo_empty1));
endmodule
//testbench for RAM
`timescale 1ns/1ns
module test2_pram;
reg [3:0]wr_addr1,rd_addr1;
reg wr_en,rd_en;
reg clk;
reg [15:0]wr_data1;
wire [15:0]rd_data1;
ram ram(.wr_ad(wr_addr1),.rd_ad(rd_addr1),.wr_en(wr_en),.rd_en(rd_en),.clk(clk),.wr_dat(wr_data1),.rd_dat(rd_data1));
initial
begin
clk=1'b0;
forever #5 clk=~clk;
end
//task for mem write
task memorywrite;
input w_e;
input [7:0]w_data;
input [3:0]w_add;
begin
@(posedge clk)
wr_en <= w_e;
wr_data1 <= w_data;
wr_addr1 <= w_add;
end
endtask
//task for mem read
task memoryread;
input r_e;
input [3:0]r_add;
input [7:0]exp_data;
begin
@(posedge clk)
rd_en <= r_e;
rd_addr1 <= r_add;
#11 if(rd_data1 != exp_data)
begin
$display("read operation failed");
$finish;
end
end
endtask
initial
begin
memorywrite(1'b1,8'h4c,4'b0000);
memorywrite(1'b1,8'h3c,4'b1000);
memorywrite(1'b1,8'h2c,4'b1110);
memoryread(1'b1,4'b1000,8'h3c);
memoryread(1'b1,4'b0000,8'h4c);
memoryread(1'b1,4'b1110,8'h2c);
#1000 $finish;
end
initial
begin
$recordfile("ram.trn");
$recordvars("depth=0");
end
endmodule
//testbench for read_write_logic
`timescale 1ns/1ns
module rd_wr_test_logic;
reg rst,clk;
reg wr_en;
reg rd_en;
wire fifo_full;
wire fifo_empty;
wire [4:0]wr_ptr;
wire [4:0]rd_ptr;
write_logic wl(.clk(clk), .rst(rst), .wr_en(wr_en), .rd_en(rd_en), .fifo_full(fifo_full), .wr_ptr(wr_ptr), .rd_ptr
(rd_ptr), .fifo_empty(fifo_empty));
initial
begin
clk=1'b0;
forever #5 clk=~clk;
end
/*initial
begin
rst = 1'b0;
#10 rst = 1'b1;
end*/
task writectrl;
input wr_en1;
input rd_en1;
input rst1;
input [4:0] exp_data;
begin
@(posedge clk or negedge rst)
wr_en = wr_en1;
rd_en = rd_en1;
rst = rst1;
#15 if(wr_ptr != exp_data)
begin
$display("write control is failed");
end
end
endtask
task readctrl;
input rd_en2;
input wr_en2;
input rst2;
input [4:0] exp_data1;
begin
@(posedge clk or negedge rst)
rd_en = rd_en2;
wr_en = wr_en2;
rst = rst2;
#15 if(rd_ptr != exp_data1)
begin
$display("read control is failed");
/*$finish;*/
end
end
endtask
initial
begin
writectrl(1'b0, 1'b0, 1'b0, 5'b00000);
writectrl(1'b1, 1'b0, 1'b1, 5'b00001);
writectrl(1'b1, 1'b0, 1'b1, 5'b00010);
writectrl(1'b1, 1'b0, 1'b1, 5'b00011);
writectrl(1'b1, 1'b0, 1'b1, 5'b00100);
writectrl(1'b1, 1'b0, 1'b1, 5'b00101);
writectrl(1'b1, 1'b0, 1'b1, 5'b00110);
writectrl(1'b1, 1'b0, 1'b1, 5'b00111);
writectrl(1'b1, 1'b0, 1'b1, 5'b01000);
writectrl(1'b1, 1'b0, 1'b1, 5'b01001);
writectrl(1'b1, 1'b0, 1'b1, 5'b01010);
writectrl(1'b1, 1'b0, 1'b1, 5'b01011);
writectrl(1'b1, 1'b0, 1'b1, 5'b01100);
writectrl(1'b1, 1'b0, 1'b1, 5'b01101);
writectrl(1'b1, 1'b0, 1'b1, 5'b01110);
writectrl(1'b1, 1'b0, 1'b1, 5'b01111);
writectrl(1'b1, 1'b0, 1'b1, 5'b01111);
readctrl(1'b1, 1'b0, 1'b0, 5'b00000);
readctrl(1'b1, 1'b0, 1'b1, 5'b00001);
readctrl(1'b1, 1'b0, 1'b1, 5'b00010);
readctrl(1'b1, 1'b0, 1'b1, 5'b00011);
readctrl(1'b1, 1'b0, 1'b1, 5'b00100);
readctrl(1'b1, 1'b0, 1'b1, 5'b00101);
readctrl(1'b1, 1'b0, 1'b1, 5'b00110);
readctrl(1'b1, 1'b0, 1'b1, 5'b00111);
readctrl(1'b1, 1'b0, 1'b1, 5'b01000);
readctrl(1'b1, 1'b0, 1'b1, 5'b01001);
readctrl(1'b1, 1'b0, 1'b1, 5'b01010);
readctrl(1'b1, 1'b0, 1'b1, 5'b01011);
readctrl(1'b1, 1'b0, 1'b1, 5'b01100);
readctrl(1'b1, 1'b0, 1'b1, 5'b01101);
readctrl(1'b1, 1'b0, 1'b1, 5'b01110);
readctrl(1'b1, 1'b0, 1'b1, 5'b01111);
#1000 $finish;
end
initial
begin
$recordfile("rd_wr_logic.trn");
$recordvars("depth=0");
end
endmodule
//testbench for fifo_top module final
`timescale 1ns/1ns
module test_fifo;
reg clk, rst;
reg [15:0]wr_data;
reg wr_enable, rd_enable;
//reg [3:0]wr_addr1;
//reg [3:0]rd_addr1;
wire [15:0]rd_data;
wire fifo_full2, fifo_empty2;
fifo_top fp(.clk(clk), .rst(rst), .wr_data(wr_data), .wr_enable(wr_enable), .rd_enable(rd_enable), .rd_data(rd_data), .fifo_full1(fifo_full2),.fifo_empty1(fifo_empty2));
initial
begin
clk=1'b0;
forever #5 clk=~clk;
end
task memory_write;
input rst1;
input w_e1;
input r_e1;
input [7:0]w_data1;
//input wr_address;
begin
@(posedge clk);
rst <=rst1;
wr_enable <= w_e1;
rd_enable <= r_e1;
wr_data <= w_data1;
//wr_
end
endtask
task memory_read;
input rst2;
input r_e1;
input w_e1;
input [7:0]exp_data;
begin
@(posedge clk);
rst <= rst2;
rd_enable <= r_e1;
wr_enable <= w_e1;
if(rd_data != exp_data)
begin
$display("read operation failed");
//$finish;
end
end
endtask
initial
begin
memory_write(1'b0,1'b1,1'b0,8'h00);
memory_write(1'b1,1'b1,1'b0,8'h01);
memory_write(1'b1,1'b1,1'b0,8'h10);
memory_write(1'b1,1'b1,1'b0,8'h12);
memory_write(1'b1,1'b1,1'b0,8'h21);
memory_write(1'b1,1'b1,1'b0,8'h45);
memory_write(1'b1,1'b1,1'b0,8'hA5);
memory_write(1'b1,1'b1,1'b0,8'h4C);
memory_write(1'b1,1'b1,1'b0,8'h1A);
memory_write(1'b1,1'b1,1'b0,8'h8F);
memory_write(1'b1,1'b1,1'b0,8'h7E);
memory_write(1'b1,1'b1,1'b0,8'h01);
memory_write(1'b1,1'b1,1'b0,8'h12);
memory_write(1'b1,1'b1,1'b0,8'h16);
memory_write(1'b1,1'b1,1'b0,8'h18);
memory_write(1'b1,1'b1,1'b0,8'h19);
memory_write(1'b1,1'b1,1'b0,8'h20);
//memory_write(1'b1,1'b1,1'b0,8'h60);
//memory_write(1'b1,1'b1,1'b0,8'h10);
memory_read(1'b1,1'b1,1'b0,8'h00);
memory_read(1'b1,1'b1,1'b0,8'h01);
memory_read(1'b1,1'b1,1'b0,8'h10);
memory_read(1'b1,1'b1,1'b0,8'h12);
memory_read(1'b1,1'b1,1'b0,8'h21);
memory_read(1'b1,1'b1,1'b0,8'h45);
memory_read(1'b1,1'b1,1'b0,8'hA5);
memory_read(1'b1,1'b1,1'b0,8'h4C);
memory_read(1'b1,1'b1,1'b0,8'h1A);
memory_read(1'b1,1'b1,1'b0,8'h8F);
memory_read(1'b1,1'b1,1'b0,8'h7E);
memory_read(1'b1,1'b1,1'b0,8'h01);
memory_read(1'b1,1'b1,1'b0,8'h12);
memory_read(1'b1,1'b1,1'b0,8'h16);
memory_read(1'b1,1'b1,1'b0,8'h18);
memory_read(1'b1,1'b1,1'b0,8'h19);
memory_read(1'b1,1'b1,1'b0,8'h20);
#200 $finish;
end
initial
begin
$recordfile("fifo_top.trn");
$recordvars("depth=0");
end
endmodule
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