verilog code for rotate bits

//rtl code for rotation

`timescale 1ns/1ns

module rotate2_4behav (a, out, out1);

parameter width = 7;

parameter rot = 2;

input [width-1:0]a;

output [width-1:0]out;

output [width-1:0]out1;

reg [width-1:0]out;

reg [width-1:0]out1;

always @(a)

begin

out = {a[rot-1:0],a[width-1:rot]};

out1 = {a[width-rot-1:0],a[width-1:width-rot]};

end

endmodule

//testbench

`timescale 1ns/1ns

module test_rotate2_4behav;

parameter width = 7;

parameter rot = 2;

reg [width-1:0]a1;

wire [width-1:0]out2;

wire [width-1:0]out3;

rotate2_4behav r1(.a(a1),

.out(out2),

.out1(out3)

);

initial

begin

a1= 7'b0011011;

#5 $display ("output = %b,%b", out2,out3);

#5 a1= 7'b0011000;

#5 $display ("output = %b,%b", out2,out3);

#5 a1= 7'b1011011;

#5 $display ("output = %b,%b", out2,out3);

#30 $finish;

end

initial

begin

$recordfile ("rotate2_4behav.trn");

$recordvars ("depth = 0");

end

endmodule