VHDL Digital N - Bit Full ADDER Logic Program

VHDL program for “N Bit Adder” behavioral design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:N Bit Adder Design    

-- Module Name:BitAdder2 - Behavioral

-- Project Name:VHDL Program for "N Bit Adder" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity BitAdder2 is

generic (N: natural :=2);

    Port ( X : in std_logic_vector(N-1 downto 0);

           Y : in std_logic_vector(N-1 downto 0);

           SUM : out std_logic_vector(N-1 downto 0);

           CARRY : out std_logic);

end BitAdder2;

architecture Behavioral of BitAdder2 is

signal result: std_logic_vector(N downto 0);

begin

            result <= ('0' & X)+('0' & Y);

            SUM <= result(N-1 downto 0);

            CARRY <= result(N);

end Behavioral;