VHDL Digital Half Substructure Logic Program

VHDL program for “Half Substructure” behavioral design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 19:09:27 03/29/12

-- Design Name: Half Substructure Design    

-- Module Name: SUB1 - Behavioral

-- Project Name:VHDL Program for "Half Substructure " in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity SUB1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           SUB : out std_logic;

           BORROW : out std_logic);

end SUB1;

architecture Behavioral of SUB1 is

begin

            process(X,Y)

            begin

                        SUB <= X XOR Y;

                        BORROW<=(NOT X) AND Y;

            end process;

end Behavioral;

VHDL program for “Half Substructure” architectural design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name: Half Substructure Design    

-- Module Name: HalfSub1 - Architectural

-- Project Name:VHDL Program for " Half Substructure " in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

----------------------------------------------------------------------------------

entity HalfSub1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           SUB : out std_logic;

           BORROW : out std_logic);

end HalfSub1;

architecture HalfSub1_arch of HalfSub1 is

begin

            process(X,Y)

            begin

                        if(X=Y) then

                                    SUB<='0';

                         end if;

                         if((X='1') and (Y='0')) then

                                    SUB<='1';

                         else

                                    BORROW<='1';

                         end if;

            end process;

end HalfSub1_arch;