VHDL Digital EX-OR Gate Program

VHDL program for “XOR Gate” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:XOR Gate Design    

-- Module Name:XOR1 - Behavioral

-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity XOR1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end XOR1;

architecture Behavioral of XOR1 is

begin

Process (X,Y)

begin

                        F <= X XOR Y;

            end process;

end Behavioral;

VHDL program for “XOR Gate” architectural design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:XOR Gate Design    

-- Module Name:XOR2 - Architectural

-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

---------------------------------------------------------------------------------

entity XOR2 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end XOR2;

architecture XOR2_arch of XOR2 is

begin

            process(X,Y)

            begin

             if(X/=Y) then

                        F<='1';

             else

                        F<='0';

             end if;

            end process;

end XOR2_arch;