VHDL Digital Half ADDER Logic Program

VHDL program for “Half Adder” behavioral design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:Half Adder Design    

-- Module Name:HalfAdder1 - Behavioral

-- Project Name:VHDL Program for "Half Adder" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity HalfAdder1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           SUM : out std_logic;

CARRY : out std_logic);

end HalfAdder1;

architecture Behavioral of HalfAdder1 is

begin

Process (X,Y)

begin

                        SUM <= X XOR Y;

                        CARRY<=X AND Y;

            end process;

end Behavioral;

VHDL program for “Half Adder” architectural design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name: HalfAdder Design    

-- Module Name: HalfAdder2 - Architectural

-- Project Name:VHDL Program for "Half Adder" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

----------------------------------------------------------------------------------

entity HalfAdder2 is

    Port ( X : in std_logic;

              Y : in std_logic;

              SUM : out std_logic;

  CARRY: out std_logic);

end HalfAdder2;

architecture HalfAdder2_arch of HalfAdder2 is

begin

            process(X,Y)

            begin

                        if(X/=Y) then

                                    SUM<='1';

                         else

                                    SUM<='0';

                         end if;

            end process;

            process(X,Y)

            begin

                         if((X='1') and (Y='1')) then

                                    CARRY<='1';

                         else

                                    CARRY<='0';

                         end if;

            end process;

end HalfAdder2_arch;