VHDL program for “JK – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:08:41 04/01/12
-- Design Name: JK FlipFlop Design
-- Module Name: JKFLIPFLOP1 - Behavioral
-- Project Name:VHDL Program for "JK FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity JKFLIPFLOP1 is
Port ( J : in std_logic;
K : in std_logic;
CLK : in std_logic;
Q : inout std_logic;
QN : inout std_logic);
end JKFLIPFLOP1;
architecture Behavioral of JKFLIPFLOP1 is
begin
process(CLK,J,K)
begin
if (CLK='1' and CLK'event) then
if(J='0' and K='0') then
Q <=Q;
QN <=QN;
elsif(J='0' and K='1') then
Q <= '1';
QN <= '0';
elsif(J='1' and K='0') then
Q <= '0';
QN <= '1';
elsif(J='1' and K='1') then
Q <= NOT Q;
QN <= NOT QN;
end if;
end if;
end process;
end Behavioral;
VHDL program for “JK – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:08:41 04/01/12
-- Design Name: JK FlipFlop Design
-- Module Name: JKFF2 - Behavioral
-- Project Name:VHDL Program for "JK FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity JKFF2 is
Port ( SN : in std_logic;
RN : in std_logic;
J : in std_logic;
K : in std_logic;
CLK : in std_logic;
Q : inout std_logic;
QN : out std_logic);
end JKFF2;
architecture Behavioral of JKFF2 is
begin
process(SN,RN,CLK)
begin
if RN='0' then
Q <= '0';
elsif SN='0' then
Q <= '1';
elsif CLK='0' and CLK'event then
q <= (J AND (NOT Q)) OR ((NOT K) AND Q);
end if;
QN <= NOT Q;
end process;
end Behavioral;
VHDL program for “JK – Flip Flop with Reset Design” Behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 10:25:40 04/02/12
-- Design Name: JK FlipFlop with Reset Design
-- Module Name: JKFF3 - Behavioral
-- Project Name:VHDL Program for "JK FlipFlop with Reset Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity JKFF3 is
Port ( CLOCK : in std_logic;
J : in std_logic;
K : in std_logic;
RESET : in std_logic;
Q : out std_logic;
QBAR : out std_logic);
end JKFF3;
architecture Behavioral of JKFF3 is
signal state: std_logic;
signal input: std_logic_vector (1 downto 0);
begin
input <= J & K;
p: process(CLOCK,RESET) is
begin
if RESET = '1' then
state <= '0';
elsif (rising_edge(CLOCK)) then
case (input) is
when"11" =>
state <= not state;
when"10" =>
state <= '1';
when"01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
end Behavioral;
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