VHDL Digital Full SUBSTRUCTURE Logic Program

VHDL program for “Full Substructure” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:19:26:12 03/29/12

-- Design Name: Full Substructure Design    

-- Module Name: SUB2 - Behavioral

-- Project Name:VHDL Program for " Full Substructure " in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity SUB2 is

    Port ( X : in std_logic;

           Y : in std_logic;

           BORROWIN : in std_logic;

           SUB : out std_logic;

           BORROWOUT : out std_logic);

end SUB2;

architecture Behavioral of SUB2 is

begin

            process (X,Y,BORROWIN)

            begin

                        SUB <= X XOR Y XOR BORROWIN;

BORROWOUT <= ((NOT X)AND Y)OR ((NOT X)AND BORROWIN) OR (Y AND BORROWIN);

            end process;

end Behavioral;