VHDL Digital OR Gate Program

VHDL program for “OR Gate” behavioral design in Xilinx integrated software environment-

--------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:03:21:43 03/28/12

-- Design Name:OR Gate Design   

-- Module Name:OR1 - Behavioral

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment 

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog) 

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity OR1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end OR1;

architecture Behavioral of OR1 is

            begin

             Process (X,Y)

             begin

                        F <= X OR Y;

             end process;

end Behavioral;

VHDL program for “OR Gate” architectural design in Xilinx integrated software environment-

--------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:03:21:43 03/28/12

-- Design Name:OR Gate Design

-- Module Name:OR2 - Architectural

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity OR2 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end OR2;

architecture OR2_arch of OR2 is

begin

            process(X,Y)

            begin

             if((X='0') and (Y='0')) then

                        F<='0';

             else

                        F<='1';

             end if;

            end process;

end OR2_arch;