VHDL Digital 1 - Bit ADDER logic Program

VHDL program for “1 Bit Adder” architectural design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:1 Bit Adder Design    

-- Module Name:BitAdder1 - Behavioral

-- Project Name:VHDL Program for "1Bit Adder" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity BitAdder1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           CIN : in std_logic;

           SUM : out std_logic;

           CARRY : out std_logic);

end BitAdder1;

architecture BitAdder1_arch of BitAdder1 is

begin

            process(X,Y)

            begin

                        if (CIN='0') then

                        if ((X AND Y)='1') then

                                    SUM <='0';

                                    CARRY <= '1';

                        elsif ((X OR Y)='1') then

                                    SUM <='1';

                                    CARRY <='0';

                        end if;

                        elsif (CIN='1') then

                        if ((X AND Y)='1') then

                                    SUM <='1';

                                    CARRY <= '1';

                        elsif ((X OR Y)='1') then

                                    SUM <='0';

                                    CARRY <='1';

                        end if;

                        end if;

            end process;

end BitAdder1_arch;