VHDL Digital NOT Gate Program

VHDL program for “NOT Gate” behavioral design in Xilinx integrated software environment-

--------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 20:19:26 03/28/12

-- Design Name:NOT Gate Design

-- Module Name:NOT1 - Behavioral

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity NOT1 is

    Port ( X : in std_logic;

           F : out std_logic);

end NOT1;

architecture Behavioral of NOT1 is

begin

Process (X)

begin

                        F <= NOT X;

            end process;

end Behavioral;

VHDL program for “NOT Gate” architectural design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:19:26 03/28/12

-- Design Name:NOT Gate Design

-- Module Name:NOT2 - Architectural

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

---------------------------------------------------------------------------------

entity NOT2 is

    Port ( X : in std_logic;

           F : out std_logic);

end NOT2;

architecture NOT2_arch of NOT2 is

begin

            process(X)

            begin

             if(X='1') then

                        F<='0';

             else

                        F<='1';

             end if;

            end process;

end NOT2_arch;