VHDL Digital 8 - Bit SUBSTRUCTURE Logic Program

VHDL program for “8 Bit Substructure” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:8 Bit Substructure  Design    

-- Module Name: SUB4 - Behavioral

-- Project Name:VHDL Program for "8 Bit Substructure " in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity SUB4 is

generic(N: natural :=2);

    Port ( X : in std_logic_vector (7 downto 0);

           Y : in std_logic_vector (7 downto 0);

           SUB : out std_logic_vector (7 downto 0);

           BORROW : out std_logic);

end SUB4;

architecture Behavioral of SUB4 is

signal result: std_logic_vector (8 downto 0);

begin

            result<=('0' & X)-('0' & Y);      

            SUB <= result(7 downto 0);

            BORROW <= result(8);

end Behavioral;