VHDL Digital AND Gate Program

VHDL program for “AND Gate” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:17:37:18 03/28/12

-- Design Name:AND Gate Design

-- Module Name:AND1 - Behavioral

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

-------------------------------------------------------------------------------

entity AND1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end AND1;

architecture Behavioral of AND1 is

begin

Process (X,Y)

begin

                        F <= X AND Y;

            end process;

end Behavioral;

VHDL program for “AND Gate” architectural design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:03:21:43 03/28/12

-- Design Name:AND Gate Design

-- Module Name:AND2 - Architectural

-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

-------------------------------------------------------------------------------

entity AND2 is

    Port ( X : in std_logic;

           Y : in std_logic;

           F : out std_logic);

end AND2;

architecture AND2_arch of AND2 is

begin

            process(X,Y)

            begin

             if((X='1') and (Y='1')) then

                        F<='1';

             else

                        F<='0';

             end if;

            end process;

end AND2_arch;