VHDL Digital Full ADDER Logic using NAND Gate Program

VHDL program for “Full Adder” design using NAND Gate in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:23:35:46 03/28/12

-- Design Name:Full Adder Design       

-- Module Name:nand2 - Behavioral

-- Project Name:VHDL Program for "Full Adder" using NAND Gate in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity nand2 is

    Port ( L : in std_logic;

           M : in std_logic;

           N : out std_logic);

end nand2;

architecture Behavioral of nand2 is

begin

            Process (L,M)

            begin

                        N <= L NAND M;

            end process;

end Behavioral;

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:23:21:04 03/28/12

-- Design Name:Full Adder Design       

-- Module Name:FullAdder2 - Structure

-- Project Name:VHDL Program for "Full Adder" using NAND Gate in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity FullAdder2 is

    Port ( X : in std_logic;

           Y : in std_logic;

           CIN : in std_logic;

           SUM : out std_logic;

           CARRY : out std_logic);

end FullAdder2;

architecture Structure of FullAdder2 is

component NAND2

    Port ( L : in std_logic;

           M : in std_logic;

           N : out std_logic);

end component;

signal T1, T2, T3, T4, T5, T6, T7: std_logic;

begin

            N1 : NAND2 Port map(X,Y,T1);

            N2 : NAND2 Port map(X,T1,T2);

            N3 : NAND2 Port map(Y,T1,T3);

            N4 : NAND2 Port map(T2,T3,T4);

            N5 : NAND2 Port map(T4,T5,T6);

            N6 : NAND2 Port map(T4,T5,T6);

            N7 : NAND2 Port map(T6,T7,T7);

            N8 : NAND2 Port map(T6,T7,SUM);

            N9 : NAND2 Port map(T1,T5,CARRY);

end Structure;