VHDL Digital OCT:BIN ENCODER Logic Program

VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment-

-------------------------------------------------------------------------------

-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 14:31:54 04/01/12

-- Design Name: Octal To Binary Encoder Design    

-- Module Name: OCT2BIN - Behavioral

-- Project Name:VHDL Program for " Octal To Binary Encoder Design" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

--------------------------------------------------------------------------------

entity OCT2BIN is

    Port ( D : in std_logic_vector (7 downto 0);

           Y : out std_logic_vector (2 downto 0));

end OCT2BIN;

architecture Behavioral of OCT2BIN is

begin

            Y(0) <= D(1) OR D(3) OR D(5) OR D(7);

            Y(1) <= D(2) OR D(3) OR D(6) OR D(7);

            Y(2) <= D(4) OR D(5) OR D(6) OR D(7);

end Behavioral;