VHDL Digital Full ADDER Logic Program

VHDL program for “Full Adder” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date:20:36:38 03/28/12

-- Design Name:Full Adder Design    

-- Module Name:FullAdder1 - Behavioral

-- Project Name:VHDL Program for "Full Adder" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity FullAdder1 is

    Port ( X : in std_logic;

           Y : in std_logic;

           CIN : in std_logic;

           SUM : out std_logic;

           CARRY : out std_logic);

end FullAdder1;

architecture Behavioral of FullAdder1 is

begin

            Process (X,Y,CIN)

            begin

                        SUM <= X XOR Y XOR CIN;

                        CARRY<=(X AND Y) OR (X AND CIN) OR (Y AND CIN);

            end process;

end Behavioral;