VHDL Digital T - Flip Flop Program

VHDL program for “T – Flip Flop Design” Behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 11:35:16 04/02/12

-- Design Name: T FlipFlop Design  

-- Module Name: TFF1 - Behavioral

-- Project Name:VHDL Program for "T FlipFlop Design" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity TFF1 is

    Port ( T : in std_logic;

           CLOCK : in std_logic;

           Q : inout std_logic;

           QN : inout std_logic);

end TFF1;

architecture Behavioral of TFF1 is

begin

            process(CLOCK,T)

            begin

                        if (CLOCK = '1' and CLOCK'event) then

                        if (T='1')then

                        Q <= NOT Q;

                        QN <= NOT Q after 0.5ns;

                        else

                        Q <= Q;

                        QN <= NOT Q after 0.5ns;

                        end if;

                        end if;

            end process;

end Behavioral;

VHDL program for “T – Flip Flop Design” Behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 12:00:24 04/02/12

-- Design Name: T FlipFlop Design  

-- Module Name: TFF2 - Behavioral

-- Project Name:VHDL Program for "T FlipFlop Design" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity TFF2 is

    Port ( T : in std_logic;

           CLOCK : in std_logic;

           Q : inout std_logic;

           QN : out std_logic);

end TFF2;

architecture Behavioral of TFF2 is

begin

             process(CLOCK)

             begin

                        if (CLOCK = '0' and CLOCK'event) then

                        Q <= (T AND (NOT Q)) OR ((NOT T) AND Q) after 10ns;

                        end if;

             QN <= NOT Q;

             end process;

end Behavioral;