VHDL Digital PARITY ENCODER Logic Program

VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment-

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-- Company:Techno Global - Balurghat

-- Engineer:Mr. Jitaditya Mondal

-- Create Date: 12:13:00 03/30/12

-- Design Name: Parity Encoder Design    

-- Module Name: ENC4 - Behavioral

-- Project Name:VHDL Program for " Parity Encoder Design" in XILINX Integrated Software Environment

-- Target Device:XC2S15

-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity ENC4 is

    Port ( W : in std_logic;

           X : in std_logic;

           Y : in std_logic;

           Z : in std_logic;

           OUTP : out std_logic;

           OUT1 : out std_logic;

           OUT2 : out std_logic);

end ENC4;

architecture Behavioral of ENC4 is

begin

            process (W,X,Y,Z)

            begin

                        OUTP <= W OR X OR Y OR Z;

                        OUT1 <= X OR Z;

                        OUT2 <= Y OR Z;

            end process;

end Behavioral;